In computer systems, hardware failures can cause erroneous processing results, such as database corruption, if the failure is undetected. In large computer system networks, the impact of undetected failures is especially severe, since for example, databases maintained on large networks can be very large and can be very difficult to reconstruct.
Hardware signature analysis has been used in processor development to detect failures. In signature analysis, a set of known inputs is dynamically applied to hardware being tested. The outputs of the hardware are then compacted into a signature by a predetermined hardware circuit such as a linear feedback shift register. The signature of the hardware under test can then be compared with a good signature to detect faults in the tested hardware. If the hardware under test is faulty, then the signature obtained will not match that of the known good signature.
It is also known to use such hardware signature analysis in a computer network at run time by running identical applications in a lock step manner on two nodes, and comparing the results. However, the constraint that the two nodes run the code in a synchronized fashion has an impact on normal processing in the two nodes. Therefore, a need exists, for improvements in hardware detection, particularly for large computer networks.